Haneul Park — Computer Architecture Ph.D. Student

TimelineNews

Jul 2026
Our study of capacity–latency tradeoffs in CXL memory expanders appeared in IEEE Computer Architecture Letters.
Jun 2026
Started a global internship at SK Hynix (Solution Architecture), evaluating High Bandwidth Flash for disaggregated LLM serving.
May 2026
Our gem5 optimization paper was nominated for Best Paper at ISPASS 2026.
Jan 2026
Our paper on compiler and system optimizations for the gem5 simulator was accepted to ISPASS 2026.
Dec 2025
Wrapped up a year and a half as a student researcher at Google, working on CXL tiered memory at hyperscale.
Jun 2025
Presented A4, our LLC management framework for servers with emerging I/O devices, at ISCA 2025 in Tokyo.
Jul 2024
Joined Google's Systems Research Group in Sunnyvale as a student researcher.
Aug 2023
Started my Ph.D. at UIUC, advised by Prof. Nam Sung Kim.

ResearchPublications

Under submission

Rethinking Compression for CXL Memory Expanders at Hyperscale

Haneul Park, Grant Ayers, Nam Sung Kim, Philip Levis, Brian Morris

IEEE CAL2026

Capacity–Latency Tradeoffs in CXL Memory Expander at Hyperscale

Haneul Park, Grant Ayers, Nam Sung Kim, Philip Levis, Brian Morris

Counter-intuitively, a slower and more complex compression algorithm can make a CXL memory expander both bigger and faster — the DRAM traffic it saves outweighs the decompression time it adds.

ISPASS2026Best Paper Nomination

Compiler and System Optimizations for gem5 Simulator

Haneul Park, Siddharth Agarwal, Pradyun Narkadamilli, Kiung Jung, Yongjun Park, Ipoom Jeong, Nam Sung Kim

Making architectural simulation dramatically faster — without touching simulation results — so design-space exploration stops being the bottleneck.

ISCA2025

A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices

Haneul Park, Jiaqi Lou, Sangjin Lee, Yifan Yuan, Kyoung Soo Park, Yongseok Son, Ipoom Jeong, Nam Sung Kim

High-speed I/O devices and CPU cores fight over the last-level cache in ways the ISA can't see. A4 finds the microarchitectural culprits and manages around them.

ISCA2023

DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory

Wenjing Jin, Wonsuk Jang, Haneul Park, Jongsung Lee, Soosung Kim, Jae W. Lee

An address translation layer for CXL memory pools that coalesces cold and unallocated regions, unlocking rank-level DRAM power-down with zero software changes.

IndustryExperience

SK Hynix · Global Internship, Solution Architecture · Bundang, Korea Jun 2026 – Present

Evaluating High Bandwidth Flash (HBF) in attention/FFN-disaggregated LLM serving systems.
Google · Student Researcher, Systems Research Group · Sunnyvale, CA Jul 2024 – Dec 2025

First performance exploration of the OCP CXL Tiered Memory Expander with inline compression at hyperscale; built a synthetic benchmark for cold-memory access patterns in tiered memory systems.

BackgroundEducation

University of Illinois Urbana-Champaign · Ph.D. candidate, Electrical & Computer Engineering Aug 2023 – Present

Advisor: Prof. Nam Sung Kim.
Seoul National University · B.S., Electrical & Computer Engineering Mar 2018 – Aug 2023

GPA 4.17/4.3, Summa Cum Laude.

RecognitionHonors & Awards

2026Best Paper Nomination, ISPASS 2026 · Compiler and System Optimizations for gem5 Simulator
2025ISCA Student Travel Grant · ISCA
20222nd Place, Deep Learning Hardware Design Competition (AIX2022) · POLARIS — presented at IEEE AICAS 2022
2019OK Bae & Jung Scholarship · OK Foundation
2018Korea Presidential Science Scholarship · one of 120 nationwide
2017Bronze Medal, Korean Young Physicists' Tournament · Korean Physical Society
2015–16Korea Physics Olympiad National Team Selection Winter Camp · KPS